Semiconductor nonvolatile storage circuits are semiconductor storage circuits that keep on holding data stored therein even after the power has been turned off. Examples of the semiconductor nonvolatile storage circuits include a flash EEPROM (electrically erasable programmable read only memory) using a floating gate structure, an FeRAM (ferroelectric random access memory) using a ferroelectric film, and an MRAM (magnetic random access memory) using a ferromagnetic film. These semiconductor nonvolatile storage circuits are expensive because they have a special transistor structure and are made of special material. These circumstances are causing demand for less expensive semiconductor nonvolatile storage circuits.
For example, Patent Document 1 suggests the following semiconductor nonvolatile storage circuit (hereinafter referred to as a known circuit). The known circuit includes two MISFETs (metal insulator semiconductor field-effect transistors). Source terminals of the two MISFETs connect to a ground potential, whereas gate terminals thereof connect to a word line. A drain terminal of the first MISFET connects to a bit line, whereas a drain terminal of the second MISFET connects to a differential pair line of the bit line.
In this known circuit, conduction resistance of the FETs is changed by applying an intermediate voltage between a power supply potential of the gate terminal of one of the two MISFETs and the ground potential, and “0” or “1” is stored in accordance with a high or low conduction resistance of the two MISFETs.
FIG. 7 is a circuit diagram showing the known circuit. This circuit includes first and second MISFETs MNM1 and MNM2 of the same type. Source terminals of the MISFETs connect to a ground potential GND through a common line COMM, and gate terminals thereof connect to a word line WL. A drain terminal of the first MISFET MNM1 connects to a bit line BL, and a drain terminal of the second MISFET MNM2 connects to a differential pair line BL_ of the bit line BL. A state where a threshold voltage Vt (MNM1) of the first MISFET MNM1 is higher than a threshold voltage Vt (MNM2) of the second MISFET MNM2 is a “0” storage state, and the opposite state is a “1” storage state.
The “type” means a distinction between n-channel-type and p-channel-type, and “the MISFETs of the same type” means that the “type” of those MISFETs is n-channel-type or p-channel-type (this is the same for the description below). Herein, the first and second MISFETs MNM1 and MNM2 are n-type MISFETs.
FIG. 8 is a timing chart showing a writing procedure in the known circuit. Writing in the known circuit is performed in the following manner. First, a state where the voltage of the word line WL is 2.5 V: about half of a power supply voltage (VDD), where the voltage of the bit line BL is 5 V: the same as the power supply voltage (VDD), and where the voltage of the differential pair line BL_ is 0 V (GND), is maintained for a predetermined period. Accordingly, only the first MISFET MNM1 operates in a saturation region, so that hot carriers are generated in the first MISFET MNM1 and the conduction resistance thereof increases. As a result, the threshold voltage Vt (MNM1) of the first MISFET MNM1 rises to become higher than the threshold voltage Vt (MNM2) of the second MISFET MNM2, and the “0” storage state occurs. On the other hand, if a state where the voltage of the bit line BL is 0 V (GND), where the voltage of the differential pair line BL_ is 5 V (VDD), and where the voltage of the word line WL is 2.5 V, is maintained for a predetermined period, the conduction resistance of the second MISFET MNM2 increases and the threshold voltage Vt (MNM2) of the second MISFET MNM2 rises. As a result, the threshold voltage Vt (MNM1) of the first MISFET MNM1 becomes lower than the threshold voltage Vt (MNM2) of the second MISFET MNM2, and the “1” storage state occurs. The amount of shift in the threshold voltage Vt may have at least a level distinguishable by the ability of a reading circuit.
FIG. 9 is an illustration of a principle of overwriting in the known circuit. The left vertical axis indicates the threshold voltage Vt (MNM1) of the first MISFET MNM1, and the right vertical axis indicates the threshold voltage Vt (MNM2) of the second MISFET MNM2. In an initial stage (before writing), the threshold voltage Vt (MNM1) and the threshold voltage Vt (MNM2) are equal to each other at Vt0. As described above, when the first MISFET MNM1 is operated in the saturation region, the threshold voltage Vt (MNM1) shifts to Vt1, which is higher than the threshold voltage Vt (MNM2) (=Vt0) of the second MISFET MNM2. Accordingly, the “0” storage state occurs. Then, the second MISFET MNM2 is allowed to operate in the saturation region so that the threshold voltage Vt (MNM2) shifts to Vt2, which is higher than Vt1. Accordingly, the “0” storage state changes to the “1” storage state. Again, the first MISFET MNM1 is allowed to operate in the saturation region so that the threshold voltage Vt (MNM1) shifts from Vt1 to Vt3. Accordingly, the “1” storage state changes to the “0” storage state. In this way, every time the MISFET of the lower threshold voltage is allowed to operate in the saturation region and the threshold voltage thereof shifts to a level higher than that of the threshold voltage of the other MISFET, the “0” storage state and the “1” storage state are switched therebetween (note that, the switching is impossible after the conduction resistance has increased and the threshold voltage does not shift any more). Since change in the threshold voltage depends on change of elements, the “0” or “1” storage state is maintained even after the power is turned off.
FIG. 10 is a timing chart illustrating a reading operation in the known circuit. Reading in the known circuit is performed in the following manner. First, the voltage of the bit line BL is set to the power supply voltage (VDD) in advance. Then, the voltage of the word line WL is raised to the power supply voltage (VDD), the first and second MISFETs MNM1 and MNM2 are brought into conduction at the same time, a difference between the threshold voltages of the MISFETs is read as a difference between the voltage of the bit line BL and the voltage of the differential pair line BL_, and then “0” or “1” is determined.
When information of a plurality of bits is to be written or read by arranging a plurality of known circuits, the following configuration is applied. FIG. 11 shows an example of a storage circuit including a plurality of known circuits. This storage circuit includes four known circuits arranged in two rows and two columns, so that information of four bits can be written/read. In this circuit, two word lines WL0 and WL1 and two pairs of bit lines BL0 and BL0_ and BL1 and BL1_ are shared by the two known circuits arranged in the row direction and the column direction, respectively.
Alternatively, a volatile storage circuit may be combined with the known circuit. In that case, information stored in the known circuit is written in the volatile storage circuit when the power is turned on, information is read or rewritten from/in the volatile storage circuit while the power is on, and the information stored in the volatile circuit is written in the known circuit before turning off the power.
FIG. 12 shows a combination of the volatile storage circuit and the known circuit. In this example, the known circuit SC connects to storage nodes C and C_ of the static semiconductor memory SM.
The static semiconductor memory SM is a known static semiconductor memory (SRAM: static random access memory). A flip-flop is constituted by cross connection of a first inverter circuit including an n-type driving transistor MN1 and a p-type load transistor MP1 and a second inverter circuit including an n-type driving transistor MN2 and a p-type load transistor MP2, and data of “1” or “0” is stored in the storage nodes C and C_.
The storage nodes C and C_ connect to a pair of bit lines BL and BL_ via transfer transistors MNT1 and MNT2, respectively. Gate terminals of the transfer transistors MNT1 and MNT2 connect to a word line WL. The paths between the storage nodes C and C_ and the pair of bit lines BL and BL_ are electrically opened/closed by a signal of the word line WL.
The known circuit SC includes the first MISFET MNM1 forming a source-drain path between the storage node C of the static semiconductor memory SM and a ground potential (GND) and the second MISFET MNM2 forming a source-drain path between the storage node C_ and the ground potential (GND). Gate terminals of the first and second MISFETs MNM1 and MNM2 connect to a word line WLW.
A transistor MPEQ is a switching element to open/close the connection between the storage nodes C and C_ by using a signal line EQ. A transistor MNRS is a switching element to open/close the connection between the driving transistors MN1 and MN2 and the ground potential GND by using a signal line RESTORE.
With this configuration, the storage circuit shown in FIG. 12 functions as a static semiconductor memory (SRAM) if a RESTORE signal is at a power supply potential, if a WLW signal is at a ground potential, and if an EQ signal is at the power supply potential. On the other hand, the storage circuit shown in FIG. 12 functions as a semiconductor nonvolatile storage circuit equivalent to the known circuit shown in FIG. 7 if the RESTORE signal is at the ground potential, if the WLW signal is at the power supply potential, and if the EQ signal is at the ground potential.
Patent Document 1: International Publication No. WO2004/057621